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ESMT
Flash
FEATURES
Single supply voltage 2.7~3.6V Standard, Dual and Quad SPI
(Preliminary)
F25L32QA
3V Only 32 Mbit Serial Flash Memory with Dual and Quad
Speed - Read max frequency: 33MHz - Fast Read max frequency: 50MHz / 86MHz/ 100MHz - Fast Read Dual/Quad max frequency: 50MHz / 100MHz (100MHz / 172MHz/ 200MHz equivalent Dual SPI; 200MHz / 344MHz/ 400MHz equivalent Quad SPI) Low power consumption - Active current: 35 mA - Standby current: 30 A - Deep Power Down current: 5 A Reliability - 100,000 typical program/erase cycles - 20 years Data Retention Program - Byte programming time: 7 s (typical) - Page programming time: 1.5 ms (typical)
Erase - Chip erase time 25 sec (typical) - Block erase time 1 sec (typical) - Sector erase time 90 ms (typical) Page Programming - 256 byte per programmable page Auto Address Increment (AAI) WORD Programming - Decrease total chip programming time over Byte Program operations Lockable 2K bytes OTP security sector SPI Serial Interface - SPI Compatible: Mode 0 and Mode 3 End of program or erase detection Write Protect ( WP ) Hold Pin ( HOLD ) All Pb-free products are RoHS-Compliant
ORDERING INFORMATION
Product ID F25L32QA -50PAG F25L32QA -86PAG F25L32QA -100PAG F25L32QA -50PHG F25L32QA -86PHG F25L32QA -100PHG Speed 50MHz 86MHz 100MHz 50MHz 86MHz 100MHz Package 8 lead SOIC 8 lead SOIC 8 lead SOIC 16 lead SOIC 16 lead SOIC 16 lead SOIC 200mil 200mil 200mil 300mil 300mil 300mil Comments Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free
GENERAL DESCRIPTION
The F25L32QA is a 32Megabit, 3V only CMOS Serial Flash memory device. The device supports the standard Serial Peripheral Interface (SPI), and a Dual/Quad SPI. ESMT's memory devices reliably store memory data even after 100,000 programming and erase cycles. The memory array can be organized into 16,384 programmable pages of 256 byte each. 1 to 256 byte can be programmed at a time with the Page Program instruction. The device also can be programmed to decrease total chip programming time with Auto Address Increment (AAI) programming. The device features sector erase architecture. The memory array is divided into 1024 uniform sectors with 4K byte each; 64 uniform blocks with 64K byte each. Sectors can be erased individually without affecting the data in other sectors. Blocks can be erased individually without affecting the data in other blocks. Whole chip erase capabilities provide the flexibility to revise the data in the device. The device has Sector, Block or Chip Erase but no page erase. The sector protect/unprotect feature disables both program and erase operations in any combination of the sectors of the memory.
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PIN CONFIGURATIONS
(Preliminary)
F25L32QA
8-PIN SOIC
CE
1
8
VDD
SO / SIO1
2
7
HOLD / SIO3
WP / SIO2
3
6
SCK
VSS
4
5
SI / SIO0
16-PIN SOIC
HOLD / SIO3 VDD
1 2
16 15
SCK SI / SIO0
NC NC
3 4
14 13
NC
NC
NC NC
5 6
12 11
NC NC
CE SO / SIO1
7 8
10 9
VSS WP / SIO2
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ESMT
PIN DESCRIPTION
Symbol SCK Pin Name Serial Clock Serial Data Input / Serial Data Input Output 0
(Preliminary)
F25L32QA
Functions To provide the timing for serial input and output operations To transfer commands, addresses or data serially into the device. Data is latched on the rising edge of SCK (for Standard read mode). / Bidirectional IO pin to transfer commands, addresses or data serially into the device on the rising edge of SCK and read data or status from the device on the falling edge of SCK(for Dual/Quad mode). To transfer data serially out of the device. Data is shifted out on the falling edge of SCK (for Standard read mode). / Bidirectional IO pin to transfer commands, addresses or data serially into the device on the rising edge of SCK and read data or status from the device on the falling edge of SCK (for Dual/Quad mode). To activate the device when CE is low. The Write Protect ( WP ) pin is used to enable/disable BPL bit in the status register. / Bidirectional IO pin to transfer commands, addresses or data serially into the device on the rising edge of SCK and read data or status from the device on the falling edge of SCK (for Quad mode). To temporality stop serial communication with SPI flash memory without resetting the device. / Bidirectional IO pin to transfer commands, addresses or data serially into the device on the rising edge of SCK and read data or status from the device on the falling edge of SCK (for Quad mode). To provide power.
SI / SIO0
SO / SIO1
Serial Data Output / Serial Data Input Output 1 Chip Enable Write Protect / Serial Data Input Output 2
CE
WP / SIO2
HOLD / SIO3 VDD VSS
Hold / Serial Data Input Output 3 Power Supply Ground
FUNCTIONAL BLOCK DIAGRAM
Page Address Latch / Counter High Voltage Generator
Memory Array
Page Buffer
Status Register Byte Address Latch / Counter Y-Decoder
Command and Conrol Logic Serial Interface
CE
SCK
SI (SIO0)
SO WP HOLD (SIO1) (SIO2) (SIO3)
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SECTOR STRUCTURE
(Preliminary)
F25L32QA
Table 1: F25L32QA Sector Address Table
Block Sector 1023 63 : 1008 1007 62 : 992 991 61 : 976 975 60 : 960 959 59 : 944 943 58 : 928 927 57 : 912 911 56 : 896 895 55 : 880 879 54 : 864 863 53 : 848 847 52 : 830 831 51 : 816 Sector Size (Kbytes) 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB Address range 3FF000H - 3FFFFFH : 3F0000H - 3F0FFFH 3EF000H - 3EFFFFH : 3E0000H - 3E0FFFH 3DF000H - 3DFFFFH : 3D0000H - 3D0FFFH 3CF000H - 3CFFFFH : 3C0000H - 3C0FFFH 3BF000H - 3BFFFFH : 3B0000H - 3B0FFFH 3AF000H - 3AFFFFH : 3A0000H - 3A0FFFH 39F000H - 39FFFFH : 390000H - 390FFFH 38F000H - 38FFFFH : 380000H - 380FFFH 37F000H - 37FFFFH : 370000H - 370FFFH 36F000H - 36FFFFH : 360000H - 360FFFH 35F000H - 35FFFFH : 350000H - 350FFFH 34F000H - 34FFFFH : 340000H - 340FFFH 33F000H - 33FFFFH : 330000H - 330FFFH 1 1 0 0 1 1 1 1 0 1 0 0 1 1 0 1 0 1 1 1 0 1 1 0 1 1 0 1 1 1 1 1 1 0 0 0 1 1 1 0 0 1 1 1 1 0 1 0 1 1 1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 Block Address A21 A20 A19 A18 A17 A16
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Block Sector 815 50 : 800 799 49 : 784 783 48 : 768 767 47 : 752 751 46 : 736 735 45 : 720 719 44 : 704 703 43 : 688 687 42 : 672 671 41 : 656 655 40 : 640 639 39 : 624 623 38 : 608 Sector Size (Kbytes) 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB
(Preliminary)
Table 1: F25L32QA Sector Address Table - Continued I
Address range 32F000H - 32FFFFH : 320000H - 320FFFH 31F000H - 31FFFFH : 310000H - 310FFFH 30F000H - 30FFFFH : 300000H - 300FFFH 2FF000H - 2FFFFFH : 2F0000H - 2F0FFFH 2EF000H - 2EFFFFH : 2E0000H - 2E0FFFH 2DF000H - 2DFFFFH : 2D0000H - 2D0FFFH 2CF000H - 2CFFFFH : 2C0000H - 2C0FFFH 2BF000H - 2BFFFFH : 2B0000H - 2B0FFFH 2AF000H - 2AFFFFH : 2A0000H - 2A0FFFH 29F000H - 29FFFFH : 290000H - 290FFFH 28F000H - 28FFFFH : 280000H - 280FFFH 27F000H - 27FFFFH : 270000H - 270FFFH 26F000H - 26FFFFH : 260000H - 260FFFH 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 Block Address A21 A20 A19 A18
F25L32QA
A17 1
A16 0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
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Block Sector 607 37 : 592 591 36 : 576 575 35 : 560 559 34 : 544 543 33 : 528 527 32 : 512 511 31 : 496 495 30 : 480 479 29 : 464 463 28 : 448 447 27 : 432 431 26 : 416 415 25 : 400 Sector Size (Kbytes) 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB
(Preliminary)
Table 1: F25L32QA Sector Address Table - Continued II
Address range 25F000H - 25FFFFH : 250000H - 250FFFH 24F000H - 24FFFFH : 240000H - 240FFFH 23F000H - 23FFFFH : 230000H - 230FFFH 22F000H - 22FFFFH : 220000H - 220FFFH 21F000H - 21FFFFH : 210000H - 210FFFH 20F000H - 20FFFFH : 200000H - 200FFFH 1FF000H - 1FFFFFH : 1F0000H - 1F0FFFH 1EF000H - 1EFFFFH : 1E0000H - 1E0FFFH 1DF000H - 1DFFFFH : 1D0000H - 1D0FFFH 1CF000H - 1CFFFFH : 1C0000H - 1C0FFFH 1BF000H - 1BFFFFH : 1B0000H - 1B0FFFH 1AF000H - 1AFFFFH : 1A0000H - 1A0FFFH 19F000H - 19FFFFH : 190000H - 190FFFH 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 0 1 1 1 0 1 1 1 0 1 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 Block Address A21 A20 A19 A18
F25L32QA
A17 0
A16 1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
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Block Sector 399 24 : 384 383 23 : 368 367 22 : 352 351 21 : 336 335 20 : 320 319 19 : 304 303 18 : 288 287 17 : 272 271 16 : 256 255 15 : 240 239 14 : 224 223 13 : 208 207 12 : 192 Sector Size (Kbytes) 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB
(Preliminary)
Table 1: F25L32QA Sector Address Table - Continued III
Address range 18F000H - 18FFFFH : 180000H - 180FFFH 17F000H - 17FFFFH : 170000H - 170FFFH 16F000H - 16FFFFH : 160000H - 160FFFH 15F000H - 15FFFFH : 150000H - 150FFFH 14F000H - 14FFFFH : 140000H - 140FFFH 13F000H - 13FFFFH : 130000H - 130FFFH 12F000H - 12FFFFH : 120000H - 120FFFH 11F000H - 11FFFFH : 110000H - 110FFFH 10F000H - 10FFFFH : 100000H - 100FFFH 0FF000H - 0FFFFFH : 0F0000H - 0F0FFFH 0EF000H - 0EFFFFH : 0E0000H - 0E0FFFH 0DF000H - 0DFFFFH : 0D0000H - 0D0FFFH 0CF000H - 0CFFFFH : 0C0000H - 0C0FFFH 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 Block Address A21 A20 A19 A18
F25L32QA
A17 0
A16 0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
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Block Sector 191 11 : 176 175 10 : 160 159 9 : 144 143 8 : 128 127 7 : 112 111 6 : 96 95 5 : 80 79 4 : 64 63 3 : 48 47 2 : 32 31 1 : 16 15 0 : 0 Sector Size (Kbytes) 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB 4KB : 4KB
(Preliminary)
Table 1: F25L32QA Sector Address Table - Continued IV
Address range 0BF000H - 0BFFFFH : 0B0000H - 0B0FFFH 0AF000H - 0AFFFFH : 0A0000H - 0A0FFFH 09F000H - 09FFFFH : 090000H - 090FFFH 08F000H - 08FFFFH : 080000H - 080FFFH 07F000H - 07FFFFH : 070000H - 070FFFH 06F000H - 06FFFFH : 060000H - 060FFFH 05F000H - 05FFFFH : 050000H - 050FFFH 04F000H - 04FFFFH : 040000H - 040FFFH 03F000H - 03FFFFH : 030000H - 030FFFH 02F000H - 02FFFFH : 020000H - 020FFFH 01F000H - 01FFFFH : 010000H - 010FFFH 00F000H - 00FFFFH : 000000H - 000FFFH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 Block Address A21 A20 A19 A18
F25L32QA
A17 1
A16 1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
1
1
1
0
0
1
0
0
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STATUS REGISTER
(Preliminary)
F25L32QA
The software status register provides status on whether the flash memory array is available for any Read or Write operation, whether the device is Write enabled, and the state of the memory Write protection. During an internal Erase or Program operation,
the status register may be read only to determine the completion of an operation in progress. Table 2 describes the function of each bit in the software status register.
Table 2: Software Status Register
Bit Name Function 1 = Internal Write operation is in progress 0 = No internal Write operation is in progress 1 = Device is memory Write enabled 0 = Device is not memory Write enabled Indicate current level of block write protection (See Table 3) Indicate current level of block write protection (See Table 3) Indicate current level of block write protection (See Table 3) Reserved for future use Auto Address Increment Programming status 1 = AAI programming mode 0 = Page Program mode 1 = BP2,BP1,BP0 are read-only bits 0 = BP2,BP1,BP0 are read/writable Reserved for future use 1 = Quad enabled 0 = Quad disabled Reserved for future use Default at Power-up 0 0 1 1 1 0 0 0 0 0 0 Read/Write
Status Register - 1 0 1 2 3 4 5 6 7 BUSY WEL BP0 BP1 BP2 RESERVED AAI BPL R R R/W R/W R/W N/A R R/W N/A R/W N/A
Status Register - 2 8 RESERVED 9 QE
10~15 RESERVED Note: 1. Only BP0, BP1, BP2, BPL and QE are writable. 2. All register bits are volatility 3. All area are protected at power-on (BP2=BP1=BP0=1)
WRITE ENABLE LATCH (WEL)
The Write-Enable-Latch bit indicates the status of the internal memory Write Enable Latch. If this bit is set to "1", it indicates the device is Write enabled. If the bit is set to "0" (reset), it indicates the device is not Write enabled and does not accept any memory Write (Program/ Erase) commands. This bit is automatically reset under the following conditions: * * * * * * * * Power-up Write Disable (WRDI) instruction completion Page Program instruction completion Auto Address Increment (AAI) Programming is completed and reached its highest unprotected memory address Sector Erase instruction completion Block Erase instruction completion Chip Erase instruction completion Write Status Register instructions
BUSY
The BUSY bit determines whether there is an internal Erase or Program operation in progress. A "1" for the BUSY bit indicates the device is busy with an operation in progress. A "0" indicates the device is ready for the next valid operation.
Auto Address Increment (AAI)
The Auto-Address-Increment-Programming-Status bit provides status on whether the device is in AAI Programming mode or Page Program mode. The default at power up is Page Program mode.
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TOP
Protection Level 0 Upper 1/64 Upper 1/32 Upper 1/16 Upper 1/8 Upper 1/4 Upper 1/2 All Blocks
(Preliminary)
Table 3: F25L32QA Block Protection Table
F25L32QA
Status Register Bit BP2 0 0 0 0 1 1 1 1 BP1 0 0 1 1 0 0 1 1 BP0 0 1 0 1 0 1 0 1
Protected Memory Area Block Range None Block 63 Block 62~63 Block 60~63 Block 56~63 Block 48~63 Block 32~63 Block 0~63 Address Range None 3F0000H -3FFFFFH 3E0000H -3FFFFFH 3C0000H -3FFFFFH 380000H -3FFFFFH 300000H -3FFFFFH 200000H -3FFFFFH 000000H -3FFFFFH
Block Protection (BP2, BP1, BP0)
The Block-Protection (BP2, BP1, BP0) bits define the size of the memory area, as defined in Table 3, to be software protected against any memory Write (Program or Erase) operations. The Write Status Register (WRSR) instruction is used to program the BP2, BP1, BP0 bits as long as WP is high or the BlockProtection-Look (BPL) bit is 0. Chip Erase can only be executed if Block-Protection bits are all 0. After power-up, BP2, BP1 and BP0 are set to1.
Block Protection Lock-Down (BPL)
WP pin driven low (VIL), enables the Block-ProtectionLock-Down (BPL) bit. When BPL is set to 1, it prevents any further alteration of the BPL, BP2, BP1, and BP0 bits. When the WP pin is driven high (VIH), the BPL bit has no effect and its value is "Don't Care". After power-up, the BPL bit is reset to 0.
Quad Enable (QE)
When the Quad Enable bit is reset to "0" (factory default), WP and HOLD pins are enabled. When QE pin is set to "1", Quad SIO2 and SIO3 are enabled. (The QE should never be set to "1" during standard and Dual SPI operation if the WP and HOLD pins are tied directly to the VDD or VSS.)
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HOLD OPERATION
(Preliminary)
F25L32QA
HOLD pin is used to pause a serial sequence underway with the SPI flash memory without resetting the clocking sequence. To activate the HOLD mode, CE must be in active low state. The HOLD mode begins when the SCK active low state coincides with the falling edge of the HOLD signal. The HOLD mode ends when the HOLD signal's rising edge coincides with the SCK active low state. If the falling edge of the HOLD signal does not coincide with the SCK active low state, then the device enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the HOLD signal does not coincide with the SCK active low state, then the device exits in Hold mode when the SCK next reaches the active low state. See Figure 1 for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high impedance state while SI and SCK can be VIL or VIH. If CE is driven active high during a Hold condition, it resets the internal logic of the device. As long as HOLD signal is low, the memory remains in the Hold condition. To resume communication with the device, HOLD must be driven active high, and CE must be driven active low. See Figure 23 for Hold timing. The HOLD function is only available for Standard SPI and Dual SPI operation, not during Quad SPI because this pin is used for SIO3 when the QE bit of Status Register-2 is set for Quad I/O.
S CK
HO L D A ctive Ho ld A ctive Ho ld A ctive
Figure 1: HOLD Condition Waveform
WRITE PROTECTION
F25L32QA provides software Write Protection. The Write-Protect pin ( WP ) enables or disables the lock-down function of the status register. The Block-Protection bits (BP2, BP1, BP0, and BPL) in the status register provide Write protection to the memory array and the status register. When the QE bit of Status Register-2 is set for Quad I/O, the WP pin function is not available since this pin is used for SIO2. See Table 4 for Block-Protection description. Table 4: Conditions to Execute Write-Status- Register (WRSR) Instruction
WP
BPL 1 0 X
Execute WRSR Instruction Not Allowed Allowed Allowed
L L H
Write Protect Pin ( WP )
The Write-Protect ( WP ) pin enables the lock-down function of the BPL bit (bit 7) in the status register. When WP is driven low, the execution of the Write Status Register (WRSR) instruction is determined by the value of the BPL bit (see Table 4). When WP is high, the lock-down function of the BPL bit is disabled.
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INSTRUCTIONS
(Preliminary)
F25L32QA
Instructions are used to Read, Write (Erase and Program), and configure the F25L32QA. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to executing any Page Program, Auto Address Increment (AAI) Programming, Write Status Register, Sector Erase, Block Erase, or Chip Erase instructions, the Write Enable (WREN) instruction must be executed first. The complete list of the instructions is provided in Table 5. All instructions are synchronized off a high to low transition of CE . Inputs will be accepted on the rising edge of SCK starting with the most significant bit. CE must be driven
low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for Read, Read ID, Read Status Register, Read Electronic Signature instructions). Any low to high transition on CE , before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to the standby mode. Instruction commands (Op Code), addresses, and data are all input from the most significant bit (MSB) first.
Table 5: Device Operation Instruction
Operation Read Fast Read Fast Read Dual Output12,13 Fast Read Dual I/O12, 14 Fast Read Quad 12, 15 Output Fast Read Quad I/O12, 16 Sector Erase4 (4K Byte) Block Erase4, (64K Byte) Chip Erase Page Program (PP) Quad Page Program17 50MHz Auto Address Increment 5 word programming (AAI) Mode Bit Reset18 Deep Power Down (DP) ~ Read Status Register-1 (RDSR-1) 6 Read Status Register-2 (RDSR-2) 6 100MHz Enable Write Status 7 Register (EWSR) Write Status Register (WRSR) 7 Write Enable (WREN) 10 Write Disable (WRDI)/ Exit secured OTP mode Enter secured OTP mode (ENSO) Release from Deep Power Down (RDP) Read Electronic Signature (RES) 8 RES in secured OTP mode & not lock down RES in secured OTP mode & lock down Max. Freq Bus Cycle 1~3 3 4 SIN SOUT SIN SOUT A15-A8 Hi-Z A7-A0 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z A15-A8 A7-A0 A7-A0, M7-M0 DOUT0~1 A15-A8 A7-A0 DIN0 X, DOUT0~1 DOUT2~6 A15-A8 Hi-Z A7-A0 Hi-Z A15-A8 Hi-Z A7-A0 Hi-Z A15-A8 -
1 2 SIN SOUT SIN SOUT 33 MHz 03H Hi-Z A23-A16 Hi-Z 0BH Hi-Z A23-A16 Hi-Z 3BH A23-A16 BBH A23-A8 6BH A23-A16 EBH A23-A0, M7-M0 20H Hi-Z A23-A16 Hi-Z D8H Hi-Z A23-A16 Hi-Z 60H / Hi-Z C7H 02H Hi-Z A23-A16 32H ADH FFH B9h 05H 35H 50H 01H 06H 04H B1H ABH ABH ABH ABH Hi-Z
5 SIN X X SOUT DOUT0 X X cont. X cont. Hi-Z
6 SIN SOUT X DOUT1 X DOUT0 DOUT0~1 DOUT0~3 DIN1 Hi-Z
N SIN SOUT
X X
cont. cont. cont.
-
cont.
-
Hi-Z A7-A0 Hi-Z A7-A0
A23-A16 Hi-Z Hi-Z DOUT (S7-S0) DOUT (S15-S8) Hi-Z X X X
A15-A8 A15-A8 -
DIN0~3 DIN0 X X X Hi-Z 15H 35H 75H
DIN4~7 DIN1 Hi-Z -
Up to 256 Hi-Z bytes Up to 256 bytes -
Hi-Z A23-A16 Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z FFH X X DIN (S7-S0) X X X
Hi-Z A7-A0 Hi-Z -. -. X X X X X X
DIN Hi-Z (S15-S8) X X X X X X
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Operation Jedec Read ID 9 (JEDEC-ID) Read ID (RDID) 11 Max. Freq 1 SIN 9FH 50MHz 90H SOUT Hi-Z Hi-Z Hi-Z
(Preliminary)
Table 5: Device Operation Instruction - Continued
Bus Cycle 1~3 4 SOUT SIN SOUT 40H Hi-Z X 00H 01H 16H Hi-Z Hi-Z -
F25L32QA
2 SIN X 00H SOUT 8CH Hi-Z SIN X 00H -
3
5 SIN X X SOUT 8CH 15H SIN X X -
6 SOUT 15H 8CH SIN -
N SOUT -
Enable SO to output ~ 70H RY/ Status during AAI 100MHz (EBSY) Disable SO to output 80H RY/ Status during AAI (DBSY)
Hi-Z
-
-
-
-
-
-
-
-
-
-
-
-
Notes:
1. 2. 3. 4. 5. 6. 7. Operation: SIN = Serial In, SOUT = Serial Out, Bus Cycle 1 = Op Code X = Dummy Input Cycles (VIL or VIH); - = Non-Applicable Cycles (Cycles are not necessary); cont. = continuous One bus cycle is eight clock periods. Sector Earse addresses: use AMS -A12, remaining addresses can be VIL or VIH Block Earse addresses: use AMS -A16, remaining addresses can be VIL or VIH To continue programming to the next sequential address location, enter the 8-bit command, followed by the data to be programmed. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE . The Enable-Write-Status-Register (EWSR) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the EWSR instruction to make both instructions effective.
8. 9.
The Read-Electronic-Signature is continuous with on going clock cycles until terminated by a low to high transition on CE . The JEDEC-Read-ID is output first byte 8CH as manufacture ID; second byte 40H as top memory type; third byte 16H as memory capacity. 10. The Write-Enable (WREN) instruction and the Write-Status-Register (WRSR) instruction must work in conjunction of each other. The WRSR instruction must be executed immediately (very next bus cycle) after the WREN instruction to make both instructions effective. Both EWSR and WREN can enable WRSR, user just need to execute one of it. A successful WRSR can reset WREN. 11. The Manufacture ID and Device ID output will repeat continuously until CE terminates the instruction. 12. Dual and Quad commands use bidirectional IO pins. DOUT and cont. are serial data out; others are serial data in. 13. Dual output data: IO0 = (D6, D4, D2, D0), (D6, D4, D2, D0) IO1 = (D7, D5, D3, D1), (D7, D5, D3, D1)
DOUT0 DOUT1
(A6, A4, A2, A0, M6, M4, M2, M0) (A7, A5, A3, A1, M7, M5, M3, M1) Bus Cycle-3
14. M7-M0: Mode bits. Dual input address: IO0 = (A22, A20, A18, A16, A14, A12, A10, A8) IO1 = (A23, A21, A19, A17, A15, A13, A11, A9)
Bus Cycle-2
15. Quad output data: IO0 = (D4, D0), (D4, D0), (D4, D0), (D4, D0) IO1 = (D5, D1), (D5, D1), (D5, D1), (D5, D1) IO2 = (D6, D2), (D6, D2), (D6, D2), (D6, D2) IO3 = (D7, D3), (D7, D3), (D7, D3), (D7, D3)
DOUT0
DOUT1
DOUT2
DOUT3
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009 Revision: 0.2 13/42
ESMT
(Preliminary)
F25L32QA
16. M7-M0: Mode bits. Quad input address: IO0 = (A20, A16, A12, A8, A4, A0, M4, M0) IO1 = (A21, A17, A13, A9, A5, A1, M5, M1) IO2 = (A22, A18, A14, A10, A6, A2, M6, M2) IO3 = (A23, A19, A15, A11, A7, A3, M7, M3)
Bus Cycle-2
Fast Read Quad I/O data: IO0 = (X, X), (X, X), (D4, D0), (D4, D0) IO1 = (X, X), (X, X), (D5, D1), (D5, D1) IO2 = (X, X), (X, X), (D6, D2), (D6, D2) IO3 = (X, X), (X, X), (D7, D3), (D7, D3)
DOUT0 DOUT1
(D4, D0), (D4, D0), (D4, D0), (D4, D0) (D5, D1), (D5, D1), (D5, D1), (D5, D1) (D6, D2), (D6, D2), (D6, D2), (D6, D2) (D7, D3), (D7, D3), (D7, D3), (D7, D3) DOUT2 DOUT3 DOUT4 DOUT5
Bus Cycle-3
Bus Cycle-4
17. The instruction is initiated by executing command code, followed by address bits into SI (SIO0) before DIN, and then input data to bidirectional IO pins (SIO0 ~ SIO3). Quad input data: IO0 = (D4, D0), (D4, D0), (D4, D0), (D4, D0) IO1 = (D5, D1), (D5, D1), (D5, D1), (D5, D1) IO2 = (D6, D2), (D6, D2), (D6, D2), (D6, D2) IO3 = (D7, D3), (D7, D3), (D7, D3), (D7, D3)
DIN0
DIN1
DIN2
DIN3
18. This instruction is recommended when using the Dual or Quad Mode bit feature.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009 Revision: 0.2 14/42
ESMT
Read (33MHz)
(Preliminary)
F25L32QA
The Read instruction supports up to 33 MHz, it outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE . The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space, i.e. for 32Mbit density, once
the data from address location 3FFFFFH had been read, the next output will be from address location 00000H. The Read instruction is initiated by executing an 8-bit command, 03H, followed by address bits [A23 -A0]. CE must remain active low for the duration of the Read cycle. See Figure 2 for the Read sequence.
Figure 2: Read Sequence
Fast Read (50 MHz ~ 100 MHz)
The Fast Read instruction supporting up to 100 MHz is initiated by executing an 8-bit command, 0BH, followed by address bits [A23 -A0] and a dummy byte. CE must remain active low for the duration of the Fast Read cycle. See Figure 3 for the Fast Read sequence. Following a dummy byte (8 clocks input dummy cycle), the Fast Read instruction outputs the data starting from the specified address location. The data output stream is continuous through all addresses until terminated by a low to high transition on CE . The internal address pointer will automatically increment until the highest memory address is reached. Once the highest memory address is reached, the address pointer will automatically increment to the beginning (wrap-around) of the address space, i.e. for 32Mbit density, once the data from address location 3FFFFFH has been read, the next output will be from address location 000000H.
CE MODE3 SCK MODE0 012345678 15 16 23 24 31 32 39 40 47 48 55 56 63 64 71 72 80
SI MSB
0B
ADD. MSB HIGH IMPENANCE
ADD.
ADD.
X
N DOUT MSB
N+1 DOUT
N+2 DOUT
N+3 DOUT
N+4 DOUT
SO
Note : X = Dummy Byte : 8 Clocks Input Dummy (VIL or VIH)
Figure 3: Fast Read Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009 Revision: 0.2 15/42
ESMT
Fast Read Dual Output (50 MHz ~ 100 MHz)
(Preliminary)
F25L32QA
The Fast Read Dual Output (3BH) instruction is similar to the standard Fast Read (0BH) instruction except the data is output on bidirectional I/O pins (SIO0 and SIO1). This allows data to be transferred from the device at twice the rate of standard SPI devices. This instruction is for quickly downloading code from Flash to RAM upon power-up or for applications that cache codesegments to RAM for execution.
The Fast Read Dual Output instruction is initiated by executing an 8-bit command, 3BH, followed by address bits [A23 -A0] and a dummy byte. CE must remain active low for the duration of the Fast Read Dual Output cycle. See Figure 4 for the Fast Read Dual Output sequence.
CE MODE3 SCK MODE0 012345678 15 16 23 24 31 32 39 40 43 44 47 48 51 52 55 56
Dummy SIO0 MSB 3B ADD. MSB HIGH IMPENANCE ADD. ADD.
IO0 switches from In put to Ouput 6420 6420 6420 642064 DOUT N DOUT N+1 DOUT N+2 DOUT N+3 DOUT N+4
SIO1
75317531 7531 753175
Note: The input data durin g the dummy clocks is "don't care". However , the IO0 pin should be high-impefance piror to th e falling edge of the first data clock.
Figure 4: Fast Read Dual Output Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009 Revision: 0.2 16/42
ESMT
Fast Read Dual I/O (50 MHz ~ 100 MHz)
(Preliminary)
F25L32QA
The Fast Read Dual I/O (BBH) instruction is similar to the Fast Read Dual Output (3BH) instruction, but with the capability to input address bits [A23 -A0] two bits per clock. To set mode bits [M7 -M0] after the address bits [A23 -A0] can further reduce instruction overhead (See Figure 5). The upper mode bits [M7 -M4] controls the length of next Fast Read Dual I/O instruction with/without the first byte command code (BBH). The lower mode bits [M3 -M0] are "don't care".
If [M7 -M0] = "AxH", the next Fast Read Dual I/O instruction (after CE is raised and the lowered) doesn't need the command code (See Figure 6). This way let the instruction sequence reduce 8 clocks and allows to enter address immediately after CE is asserted low. If [M7 -M0] are the value other than "AxH", the next instruction need the first byte command code, thus returning to normal operation. A Mode Bit Reset (FFH) also can be used to reset mode bits [M7 -M0] before issuing normal instructions.
CE MODE3 SCK MODE0
012345678 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 27 28 31 32 35 36 39 40
IO0 switches from Input to Ouput SIO0 MSB HIG H IMPENANCE BB
22 20 18 16 14 12 10 8 6 4 2 0 6 4
642064206420 6420 64 DOUT N DOUT N+1 DOUT N+2 DOUT N+3 DOUT N+4
SIO1
23 21 19 17 15 13 11 9
7
5
3
1
7
5
753175317531 7531 75
A23-16
A15-8
A7-0
M7-0
Note: The mode bits [M3 -M0] are "d on't care". However , the IO pins sh ould be high-impefance piror to the falling edge of the first data clock.
Figure 5: Fast Read Dual I/O Sequence ([M7 -M0] = 0xH or NOT AxH)
CE MODE3 SCK MODE0 IO0 switches from In put to Ouput SIO0
22 20 18 16 14 12 10 8 6 4 2 0 6 4
6420 6420 6420 642064 DOUT N DOUT N+1 DOUT N+2 DOUT N+3 DOUT N+4
SIO1
23 21 19 17 15 13 11
9
7
5
3
1
7
5
7531 7531 7531 753175
A23-16
A15-8
A7-0
M7-0
Note: The mode bits [M3 -M0] are "don't care". However , the IO pins sh ould be high-impe fance piror to the fa ll ing edge of the fi rst data clock.
Figure 6: Fast Read Dual I/O Sequence ([M7 -M0] = AxH)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009 Revision: 0.2 17/42
ESMT
(Preliminary)
F25L32QA
Fast Read Quad Output (50 MHz ~ 100 MHz)
The Fast Read Quad Output (6B) instruction is similar to the Fast Read Dual Output (3BH) instruction except the data is output on bidirectional I/O pins (SIO0, SIO1, SIO2 and SIO3). A Quad Enable (QE) bit of Status Register-2 must be set "1" to enable Quad function. This allows data to be transferred from the device at four times the rate of standard SPI devices. The Fast Read Quad Output instruction is initiated by executing an 8-bit command, 6BH, followed by address bits [A23 -A0] and a dummy byte. CE must remain active low for the duration of the Fast Read Dual Output cycle. See Figure 7 for the Fast Read Quad Output sequence.
CE MODE3 SCK MODE0 Dummy SIO0 MSB SIO1 6B ADD. MSB HIGH IMPENANCE ADD. A DD. IO0 switches from Input to Ouput 40404040 40 012345678 15 16 23 24 31 32 39 40 4142 43 44 45 46 47 48
51515151 51
SIO2
HIGH IMPENANCE
62
SIO3
HIGH IMPENANCE
73
N N+1 N+2 N+3 N+4 DOUT DOUT DOUT DOUT DOUT
Note: The input data du ring the dummy clocks is "don't care". However , the IO pins should be high-impefance piror to the fal ling edge o f the first data clock.
Figure 7: Fast Read Quad Output Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009 Revision: 0.2 18/42
ESMT
Fast Read Quad I/O (50 MHz ~ 100 MHz)
(Preliminary)
F25L32QA
The Fast Read Quad I/O (EBH) instruction is similar to the Fast Read Quad Output (6BH) instruction, but with the capability to input address bits [A23 -A0] four bits per clock. A Quad Enable (QE) bit of Status Register-2 must be set "1" to enable Quad function. To set mode bits [M7 -M0] after the address bits [A23 -A0] can further reduce instruction overhead (See Figure 8). The upper mode bits [M7 -M4] controls the length of next Fast Read Quad I/O instruction with/without the first byte command code (EBH). The lower mode bits [M3 -M0] are "don't care".
If [M7 -M0] = "AxH", the next Fast Read Quad I/O instruction (after CE is raised and the lowered) doesn't need the command code (See Figure 9). This way let the instruction sequence reduce 8 clocks and allows to enter address immediately after CE is asserted low. If [M7 -M0] are the value other than "AxH", the next instruction need the first byte command code, thus returning to normal operation. A Mode Bit Reset (FFH) also can be used to reset mode bits [M7 -M0] before issuing normal instructions.
CE MODE3 SCK MODE0
012345678 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
Dummy SIO0 MSB SIO1 HIGH IMPE NANCE
21 17 13 9
IO0 switches from Input to Ouput 4040 40
EB
20 16 12 8
4
0
4
0
5
1
5
1
5151 51 6262 62 7373 73
N N+1 N+2 DOUT DOUT DOUT
SIO2 SIO3
HIGH IMPENANCE
HIGH IMP ENANCE
22 18 14 10
6
2
6
2
23 19 15 11
7
3
7
3
A 23- 0
M7 -0
Note: The mode bits [M3 -M0] are "don't care". However , the IO pins sh ould be high-impe fance piror to the fall ing edge of the fi rst data clock.
Figure 8: Fast Read Quad I/O Sequence ([M7 -M0] = 0xH or NOT AxH)
CE MODE3 SCK MODE0
0123 45678 9 10 11 12 13 14 15 16
Dummy SIO0
20 16 12 8 4 0 4 0
IO0 switches from Input to Oup ut 4040 40
SIO1
21 1 7 13 9
5
1
5
1
5151 51 626262 737373
N N+1 N+2 DOUT DOUT DOUT
SIO2 SIO3
22 18 14 10 6
2
6
2
23 19 15 11
7
3
7
3
A23-0
M7-0
Note: The mode bits [M3 -M0] are "don't care". However , the IO pins sh ould be high-imp efance piror to the falling edge of the fi rst data clock.
Figure 9: Fast Read Quad I/O Sequence ([M7 -M0] = AxH)
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009 Revision: 0.2 19/42
ESMT
Page Program (PP)
(Preliminary)
F25L32QA
The Page Program instruction allows many bytes to be programmed in the memory. The bytes must be in the erased state (FFH) when initiating a Program operation. A Page Program instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write Enable (WREN) instruction must be executed. CE must remain active low for the duration of the Page Program instruction. The Page Program instruction is initiated by executing an 8-bit command, 02H, followed by address bits [A23-A0]. Following the address, at least one byte Data is input (the maximum of input data can be up to 256 bytes). If the 8 least significant address bits [A7-A0] are not all zero, all transmitted data that goes beyond the end of the current page are programmed from the start address of the same page (from the address whose 8 least significant bits [A7-A0] are all zero). If more than 256 bytes Data are sent to the device, previously
latched data are discarded and the last 256 bytes Data are guaranteed to be programmed correctly within the same page. If less than 256 bytes Data are sent to device, they are correctly programmed at the requested addresses without having any effects on the other bytes of the same page. CE must be driven high before the instruction is executed. The user may poll the BUSY bit in the software status register or wait TPP for the completion of the internal self-timed Page Program operation. While the Page Program cycle is in progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY bit. It is recommended to wait for a duration of TBP1 before reading the status register to check the BUSY bit. The BUSY bit is a 1 during the Page Program cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again. After the Page Program cycle has finished, the Write-Enable-Latch (WEL) bit in the Status Register is cleared to 0. See Figure 10 for the Page Program sequence.
Figure 10: Page Program Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009 Revision: 0.2 20/42
ESMT
Quad Page Program
(Preliminary)
F25L32QA
The Quad Page Program instruction allows many bytes to be programmed in the memory by using four I/O pins (SIO0, SIO1, SIO2 and SIO3). The instruction can improve programmer performance and the effectiveness of application that have slow clock speed <20MHz. For system with faster clock, this instruction can't provide more actual favors, because the required internal page program time is far more than the time data flows in. Therefore, we suggest that user can execute this command while
the clock speed <20MHz. Prior to Quad Page Program operation, the Write Enable (WREN) instruction must be executed and Quad Enable (QE) bit of Status Register-2 must be set "1". The other function descriptions are as same as standard Page Program. See Figure 11 for the Quad Page Program sequence.
CE MODE3 SCK MODE0 012345678 15 1 6 23 24 31 32 33 34 35 36 37 3839
SS
32 MSB ADD. MSB ADD. A DD. 40404040
SIO0
SS
40
SIO1
51515151
SS
51
SIO2
SS
62
SIO3 DIN0 DIN1 DIN2 DIN3
SS
73
DIN255
Figure 11: Quad Page Program Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009 Revision: 0.2 21/42
ESMT
(Preliminary)
F25L32QA
Auto Address Increment (AAI) WORD Program
The AAI program instruction allows multiple bytes of data to be programmed without re-issuing the next sequential address location. This feature decreases total programming time when the multiple bytes or entire memory array is to be programmed. An AAI program instruction pointing to a protected memory area will be ignored. The selected address range must be in the erased state (FFH) when initiating an AAI program instruction. While within AAI WORD programming sequence, the only valid instructions are AAI WORD program operation, RDSR, WRDI. Users have three options to determine the completion of each AAI WORD program cycle: hardware detection by reading the SO; software detection by polling the BUSY in the software status register or wait TBP. Refer to End of Write Detection section for details. Prior to any write operation, the Write Enable (WREN) instruction must be executed. The AAI WORD program instruction is initiated by executing an 8-bit command, ADH, followed by address bits [A23 -A0]. Following the addresses, two bytes of data is input sequentially. The data is input sequentially from MSB (bit 7) to LSB (bit 0). The first byte of data (D0) will be programmed into the initial address [A23 -A1] with A0 =0; the second byte of data (D1) will be programmed into the initial address [A23 -A1] with A0 =1. CE must be driven high before the AAI WORD program instruction is executed. The user must check the busy status before entering the next valid command. Once the device indicates it is no longer busy, data for next two sequential addresses may be programmed and so on. When the last desired byte had been entered, check the busy status using the hardware method or the RDSR instruction and execute the WRDI instruction, to terminate AAI. User must check busy status after WRDI to determine if the device is ready for any command. Please refer to Figure 14 and Figure 15. There is no wrap mode during AAI programming; once the highest unprotected memory address is reached, the device will exit AAI operation and reset the Write-Enable-Latch bit (WEL = 0) and the AAI bit (AAI=0).
End of Write Detection
There are three methods to determine completion of a program cycle during AAI WORD programming: hardware detection by reading the SO, software detection by polling the BUSY bit in the Software Status Register or wait TBP. The Hardware End of Write Detection method is described in the section below.
Hardware End of Write Detection
The Hardware End of Write Detection method eliminates the overhead of polling the BUSY bit in the Software Status Register during an AAI Word program operation. The 8-bit command, 70H, configures the SO pin to indicate Flash busy status during AAI WORD programming (refer to Figure 12). The 8-bit command, 70H, must be executed prior to executing an AAI WORD program instruction. Once an internal programming operation begins, asserting CE will immediately drive the status of the internal flash status on the SO pin. A "0" Indicates the device is busy; a "1" Indicates the device is ready for the next instruction. De-asserting CE will return the SO pin to tri-state. The 8-bit command, 80H, disables the SO pin to output busy status during AAI WORD program operation and return SO pin to output Software Status Register data during AAI WORD programming (refer to Figure 13).
Figure 12: Enable SO as Hardware during AAI Programming
Figure 13: Disable SO as Hardware during AAI Programming
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009 Revision: 0.2 22/42
ESMT
(Preliminary)
F25L32QA
Figure 14: AAI Word Program Sequence with Hardware End of Write Detection
Figure 15: AAI Word Program Sequence with Software End of Write Detection
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009 Revision: 0.2 23/42
ESMT
Mode Bit Reset
(Preliminary)
F25L32QA
Mode bits [M7 -M0] are issued to further reduce instruction overhead for Fast Read Dual/Quad I/O operation. If [M7 -M0] = "AxH", the next Fast Read Dual/Quad I/O instruction doesn't need the command code. If the system controller is reset during operation, it will send a standard instruction (such as Read ID) to the Flash memory.
However, the device doesn't have a hardware reset pin, so if [M7 -M0] = "AxH", the device will not recognize any standard SPI instruction. After a system reset, it is recommended to issue a Mode Bit Reset instruction first to release the status of [M7 -M0] = "AxH" and allow the device to recognize standard SPI instruction. See Figure 16 for the Mode Bit Reset instruction.
Mode bit Reset for Dual I/O Mode bit Reset for Quad I/O
CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
SIO0 SIO 1
FF
FF
SIO2
SIO3
Note: To reset mode bits dur ing Quad I/O operation, only eight cl ocks are needed. The command code is "FFH". To reset mode bits durin g Dua l I/O operation, sixteen clocks are needed to shift in command code "FFFFH".
Figure 16: Mode Bit Reset Instruction
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009 Revision: 0.2 24/42
ESMT
64K Byte Block Erase
(Preliminary)
F25L32QA
The 64K-byte Block Erase instruction clears all bits in the selected block to FFH. A Block Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write Enable (WREN) instruction must be executed. CE must remain active low for the duration of the any command sequence. The Block Erase instruction is initiated by executing an 8-bit command, D8H, followed by address bits [A23
-A0]. Address bits [AMS -A16] (AMS = Most Significant address) are used to determine the block address (BAX), remaining address bits can be VIL or VIH. CE must be driven high before the instruction is executed. The user may poll the BUSY bit in the Software Status Register or wait TBE for the completion of the internal self-timed Block Erase cycle. See Figure 17 for the Block Erase sequence.
Figure 17: 64K-byte Block Erase Sequence
4K Byte Sector Erase
The Sector Erase instruction clears all bits in the selected sector to FFH. A Sector Erase instruction applied to a protected memory area will be ignored. Prior to any Write operation, the Write Enable (WREN) instruction must be executed. CE must remain active low for the duration of the any command sequence. The Sector Erase instruction is initiated by executing an 8-bit command, 20H, followed by address bits [A23 -A0]. Address bits [AMS -A12] (AMS = Most Significant address) are used to determine the sector address (SAX), remaining address bits can be VIL or VIH. CE must be driven high before the instruction is executed. The user may poll the BUSY bit in the Software Status Register or wait TSE for the completion of the internal self-timed Sector Erase cycle. See Figure 18 for the Sector Erase sequence.
CE MODE3 SCK MODE0 012345678 15 16 23 24 31
SI MSB
20
ADD. MSB HIGH IMPENANCE
ADD.
ADD.
SO
Figure 18: 4K-byte Sector Erase Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009 Revision: 0.2 25/42
ESMT
Chip Erase
(Preliminary)
F25L32QA
The Chip Erase instruction clears all bits in the device to FFH. A Chip Erase instruction will be ignored if any of the memory area is protected. Prior to any Write operation, the Write Enable (WREN) instruction must be executed. CE must remain active low for the duration of the Chip-Erase instruction sequence. The Chip
Erase instruction is initiated by executing an 8-bit command, 60H or C7H. CE must be driven high before the instruction is executed. The user may poll the BUSY bit in the Software Status Register or wait TCE for the completion of the internal self-timed Chip Erase cycle. See Figure 19 for the Chip Erase sequence.
CE MODE3 SCK MODE0 01234567
SI MSB
60 or C7
SO
HIGH IMPENANCE
Figure 19: Chip Erase Sequence
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows reading of the status register. The status register may be read at any time even during a Write (Program/Erase) operation. When a Write operation is in progress, the BUSY bit may be checked before sending any new commands to assure that the new commands are properly received by the device. CE must be driven low before the RDSR instruction is entered and remain low until the status data is read. The RDSR-1 instruction code is "05H" for Status Register-1 and RDSR-2 instruction code is "35H" for Status Register-2. Read Status Register is continuous with ongoing clock cycles until it is terminated by a low to high transition of the CE . See Figure 20 for the RDSR instruction sequence.
CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14
SI MSB SO
05 or 35 HIGH IMPEDANCE
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 MSB
Status Register -1 or -2 Data Out
Figure 20: Read Status Register (RDSR-1 or RDSR-2) Sequence
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009 Revision: 0.2 26/42
ESMT
Write Enable (WREN)
(Preliminary)
F25L32QA
The Write Enable (WREN) instruction sets the Write-EnableLatch bit in the Software Status Register to 1 allowing Write operations to occur. The WREN instruction must be executed prior to any Write
(Program/Erase) operation. CE must be driven high before the WREN instruction is executed.
CE MODE3 SCK MODE0 01234567
SI MSB
06
SO
HIGH IMPENANCE
Figure 21: Write Enable (WREN) Sequence
Write Disable (WRDI)
The Write Disable (WRDI) instruction resets the Write-EnableLatch bit to 0 disabling any new Write operations from occurring. CE must be driven high before the WRDI instruction is executed.
CE MODE3 SCK MODE0 01234567
SI MSB
04
SO
HIGH IMPENANCE
Figure 22: Write Disable (WRDI) Sequence
Enable Write Status Register (EWSR)
The Enable Write Status Register (EWSR) instruction arms the Write Status Register (WRSR) instruction and opens the status register for alteration. The Enable Write Status Register instruction does not have any effect and will be wasted, if it is not followed immediately by the Write Status Register (WRSR) instruction. CE must be driven low before the EWSR instruction is entered and must be driven high before the EWSR instruction is executed.
Elite Semiconductor Memory Technology Inc.
Publication Date: Jan. 2009 Revision: 0.2 27/42
ESMT
Write-Status-Register (WRSR)
(Preliminary)
F25L32QA
The Write Status Register instruction writes new values to the BP2, BP1, BP0, BPL (Status Register-1) and QE (Status Register-2) bits of the status register. CE must be driven low before the command sequence of the WRSR instruction is entered and driven high before the WRSR instruction is executed. CE must be driven high after the eighth or sixteenth bit of data that is clocked in. If it is not done, the WRSR instruction will not be issued. If CE is high after the eighth bits of data, the QE bit will be cleared to 0. See Figure 23 for EWSR or WREN and WRSR instruction sequences. Executing the Write Status Register instruction will be ignored when WP is low and BPL bit is set to "1". When the WP is low, the BPL bit can only be set from "0" to "1" to lock down the
status register, but cannot be reset from "1" to "0". When WP is high, the lock-down function of the BPL bit is disabled and the BPL, BP0, BP1,and BP2 bits in the status register can all be changed. As long as BPL bit is set to 0 or WP pin is driven high (VIH) prior to the low-to-high transition of the CE pin at the end of the WRSR instruction, the bits in the status register can all be altered by the WRSR instruction. In this case, a single WRSR instruction can set the BPL bit to "1" to lock down the status register as well as altering the BP0; BP1 and BP2 bits at the same time. See Table 4 for a summary description of WP and BPL functions.
CE MODE3 SCK MODE0 01234567 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 151617 1819 20 21 22 23 Stauts Register - 1 Data In SI MSB SO HIGH IMPENANCE 50 or 06 01 Stauts Register - 2 Data In
7 6 5 4 3 2 1 0 15 14 13 12 1110 9 8
MSB
Figure 23: Enable-Write-Status-Register (EWSR) or Write-Enable (WREN) and Write-Status-Register (WRSR)
Enter OTP Mode (ENSO)
The ENSO (B1H) instruction is for entering the additional 2K bytes secured OTP mode. The additional 2K bytes secured OTP sector is independent from main array, which may use to store unique serial number for system identifier. User must unprotect whole array (BP0=BP1=BP2=0), prior to any Write (Program/ Erase) operation in OTP sector. After entering the secured OTP mode, only the secured OTP sector can be accessed and user can follow the standard Read or Write procedure except for Block Erase and Chip Erase. The secured OTP data cannot be updated again once it is lock down. In secured OTP mode, WRSR command will ignore the input data and lock down the secured OTP sector (OTP_lock bit =1). To exit secured OTP mode, user must execute WRDI command. RES can be used to verify the secured OTP status as shown in Table 6.
Figure 24: Enter OTP Mode (ENSO) Sequence
Elite Semiconductor Memory Technology Inc.
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ESMT
Deep Power Down (DP)
(Preliminary)
F25L32QA
The Deep Power Down instruction is for minimizing power consumption (the standby current is reduced from ISB1 to ISB2.). This instruction is initiated by executing an 8-bit command, B9H, and then CE must be driven high. After CE is driven high, the device will enter to deep power down within the duration of TDP.
Once the device is in deep power down status, all instructions will be ignored except the Release from Deep Power Down instruction (RDP) and Read Electronic Signature instruction (RES). The device always power-up in the normal operation with the standby current (ISB1). See Figure 25 for the Deep Power Down instruction.
CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7
TDP
SI MSB
B9
Standard Current
Deep Power Down Current (ISB2)
Figure 25: Deep Power Down Instruction
Release from Deep Power Down (RDP) and Read Electronic-Signature (RES)
The Release form Deep Power Down and Read Electronic-Signature instruction is a multi-purpose instruction. The instruction can be used to release the device from the deep power down status. This instruction is initiated by driving CE low and executing an 8-bit command, ABH, and then drive CE high. See Figure 26 for RDP instruction. Release from the deep power down will take the duration of TRES1 before the device will resume normal operation and other instructions are accepted. CE must remain high during TRES1. The instruction also can be used to read the 8-bit ElectronicSignature of the device on the SO pin. It is initiated by driving CE low and executing an 8-bit command, ABH, followed by 3 dummy bytes. The Electronic-Signature byte is then output from the device. The Electronic-Signature can be read continuously until CE go high. See Figure 27 for RES sequence. After driving CE high, it must remain high during for the duration of TRES2, and then the device will resume normal operation and other instructions are accepted. The instruction is executed while an Erase, Program or WRSR cycle is in progress is ignored and has no effect on the cycle in progress. In OTP mode, user also can execute RES to confirm the status of OTP.
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ESMT
CE MODE3 SCK MODE0 0 1 2
(Preliminary)
F25L32QA
3
4
5
6
7
TRES1
SI MSB
AB
HIGH IMPEDANCE
SO
Deep Power Down Current (ISB2)
Standby Current
Figure 26: Release from Deep Power Down (RDP) Instruction
CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 8 9 30 31 32 33 34 35 36 37 38
TRES2
SS
SI MSB SO
AB
3 Dummy Bytes SS
HIGH IMPEDANCE
SS
MSB
Electronic-Signature Data Out
Deep Power Down Current (ISB2)
Standby Current
Figure 27: Read Electronic -Signature (RES) Sequence
Table 6: Electronic Signature Data Command Mode Normal RES In secured OTP mode & non lock down (OTP_lock =0) In secured OTP mode & lock down (OTP_lock =1) Electronic Signature Data 15H 35H 75H
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ESMT
JEDEC Read-ID
(Preliminary)
F25L32QA
The JEDEC Read-ID instruction identifies the device as F25L32QA and the manufacturer as ESMT. The device information can be read from executing the 8-bit command, 9FH. Following the JEDEC Read-ID instruction, the 8-bit manufacturer's ID, 8CH, is output from the device. After that, a 16-bit device ID is shifted out on the SO pin. Byte1, 8CH, identifies the manufacturer as ESMT. Byte2, 40H, identifies the memory type as SPI Flash. Byte3, 16H, identifies the device as
F25L32QA. The instruction sequence is shown in Figure 28. The JEDEC Read ID instruction is terminated by a low to high transition on CE at any time during data output. If no other command is issued after executing the JEDEC Read-ID instruction, issue a 00H (NOP) command before going into Standby Mode ( CE =VIH).
CE MODE3 SCK MODE0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 1415 1617 1819 2021 22 23 24 25 2627 2829 3031
SI MSB SO
9F
HIGH IMPENANCE MSB
8C MSB
40 MSB
16
Figure 28: JEDEC Read-ID Sequence
Table 7: JEDEC Read-ID Data Device ID Memory Type (Byte 2) 40H Memory Capacity (Byte 3) 16H
Manufacturer's ID (Byte 1) 8CH
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ESMT
Read-ID (RDID)
(Preliminary)
F25L32QA
The Read-ID instruction (RDID) identifies the devices as F25L32QA and manufacturer as ESMT. This command is backward compatible to all ESMT SPI devices and should be used as default device identification when multiple versions of ESMT SPI devices are used in one design. The device information can be read from executing an 8-bit command, 90H, followed by address bits [A23 -A0]. Following the Read-ID
instruction, the manufacturer's ID is located in address 00000H and the device ID is located in address 00001H. Once the device is in Read-ID mode, the manufacturer's and device ID output data toggles between address 00000H and 00001H until terminated by a low to high transition on CE .
CE MODE3 SCK MODE0 012345678 15 16 23 24 31 32 39 40 47 4 8 55 56 63
SI MSB
90
00
00 MSB
ADD
1
SO
HIGH IMPENANCE MSB
8C
15
8C
15
HIGH IMPENA NCE
Note: The Manufacture's an d Device ID o utput stream i s continu ous until terminated by a low to high transition on CE. 1. 00H will output the Manufacture's ID first a nd 01H will output Device ID first b efore toggling between the two. .
Figure 29: Read ID Sequence
Table 8: Product ID Data Address 00000H Byte1 8CH Manufacturer's ID 15H 00001H Device ID ESMT F25L32QA Byte2 15H Device ID ESMT F25L32QA 8CH Manufacturer's ID
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ESMT
ELECTRICAL SPECIFICATIONS
(Preliminary)
F25L32QA
Absolute Maximum Stress Ratings (Applied conditions are greater than those listed under "Absolute Maximum Stress Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these conditions or conditions greater than those defined in the operational sections of this datasheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.) Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C D. C. Voltage on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to VDD+0.5V Transient Voltage (<20 ns) on Any Pin to Ground Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0V to VDD+2.0V Package Power Dissipation Capability (TA = 25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W Surface Mount Lead Soldering Temperature (3 Seconds) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240C Output Short Circuit Current (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA ( Note 1: Output shorted for no more than one second. No more than one output shorted at a time. )
TABLE 9: AC CONDITIONS OF TEST
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ns Output Load . . . . . . . . . . . . . . . . . . . . . . . . CL = 15 pF for 75MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .CL = 30 pF for 50MHz See Figures 34 and 35
TABLE 10: OPERATING RANGE
Parameter Operating Supply Voltage VDD (FCLK > 50MHz) Ambient Operating Temperature TA 3.0 ~ 3.6 0 ~ 70 Symbol VDD Value 2.7 ~ 3.6 Unit V V
TABLE 11: DC OPERATING CHARACTERISTICS
Symbol IDDR1 Parameter Standard Dual Quad Standard Read Current Dual @ 50MHz Quad Standard Read Current Dual @ 86MHz Quad Standard Read Current Dual @ 100MHz Quad Program and Erase Current Read Current @ 33MHz Standby Current Deep Power Down Current Input Leakage Current Output Leakage Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Min Limits Max 15 18 20 20 23 25 23 25 28 25 28 30 35 30 5 1 1 0.8 0.7 x VDD 0.2 VDD-0.2 Unit mA Test Condition CE =0.1 VDD/0.9 VDD, SO=open
IDDR2
mA
CE =0.1 VDD/0.9 VDD, SO=open
IDDR3 IDDR4 IDDW ISB1 ISB2 ILI ILO VIL VIH VOL VOH
mA
CE =0.1 VDD/0.9 VDD, SO=open CE =0.1 VDD/0.9 VDD, SO=open CE =VDD CE =VDD, VIN =VDD or VSS CE =VDD, VIN =VDD or VSS VIN=GND to VDD, VDD=VDD Max VOUT=GND to VDD, VDD=VDD Max VDD=VDD Min VDD=VDD Max IOL=100 A, VDD=VDD Min IOH=-100 A, VDD=VDD Min
mA mA A A A A V V V V
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ESMT
TABLE 12: LATCH UP CHARACTERISTIC
Symbol ILTH
1
(Preliminary)
Parameter Minimum 100 + IDD Unit mA Test Method
F25L32QA
Latch Up
JEDEC Standard 78
Note 1: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 13: RECOMMENDED SYSTEM POWER-UP TIMINGS
Symbol TPU-READ
1 1
Parameter VDD Min to Read Operation VDD Min to Write Operation
Minimum 10 10
Unit s s
TPU-WRITE
TABLE 14: CAPACITANCE (TA = 25C, f=1 MHz, other pins open)
Parameter COUT
1 CIN 1
Description Output Pin Capacitance Input Capacitance
Test Condition VOUT = 0V VIN = 0V
Maximum 12 pF 6 pF
Note 1: This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
TABLE 15: AC OPERATING CHARACTERISTICS
Normal 33MHz Symbol FCLK TSCKH TSCKL TCES1 TCEH
1
Fast 50 MHz Min Max 50 9 9 5 5 5 5 100
Fast 86 MHz Min Max 86 7 7 5 5 5 5 100
Fast 100 MHz Unit Min Max 100 5 5 5 5 5 5 100 MHz ns ns ns ns ns ns ns 9 0 3 3 5 5 5 5 ns ns ns ns ns ns ns ns 9 ns
Parameter Min Serial Clock Frequency Serial Clock High Time Serial Clock Low Time CE Active Setup Time CE Active Hold Time CE Not Active Setup Time CE Not Active Hold Time CE High Time CE High to High-Z Output SCK Low to Low-Z Output Data In Setup Time Data In Hold Time HOLD Low Setup Time HOLD High Setup Time HOLD Low Hold Time HOLD High Hold Time HOLD Low to High-Z Output 0 3 3 5 5 5 5 9 13 13 5 5 5 5 100 9 0 3 3 5 5 5 5 9 Max 33
1 TCHS
TCHH1 TCPH TCHZ TCLZ TDS TDH THLS THHS THLH THHH THZ
9 0 3 3 5 5 5 5
9
9
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Symbol TLZ TOH TV TDP TRES1 TRES2 Parameter
(Preliminary)
F25L32QA
TABLE 15: AC OPERATING CHARACTERISTICS - Continued
Normal 33MHz Min HOLD High to Low-Z Output Output Hold from SCK Change Output Valid from SCK CE High to Deep Power Down Mode CE High to Standby Mode ( for DP) CE High to Standby Mode (for RES) 0 12 3 3 1.8 Max 9 0 8 3 3 1.8 Fast 50 MHz Min Max 9 0 8 3 3 1.8 Fast 86 MHz Min Max 9 0 8 3 3 1.8 Fast 100 MHz Unit Min Max 9 ns ns ns us us us
Note 1: Relative to SCK.
TABLE 16: ERASE AND PROGRAMMING PERFORMANCE
Limit Parameter Sector Erase Time Block Erase Time Chip Erase Time Byte Programming Time Page Programming Time Chip Programming Time Erase/Program Cycles1 Data Retention Notes: 1. 2. 3. Not 100% Tested, Excludes external system level over head. Typical values measured at 25C, 3V. Maximum values measured at 85C, 2.7V. Symbol Typ TSE TBE TCE TBP TPP 90 1 25 7 1.5 50 100,000 20
2
Max3 300 2 50 30 5 100 -
Unit ms s s us ms s Cycles Years
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ESMT
(Preliminary)
F25L32QA
Figure 30: Serial Input Timing Diagram
Figure 31: Serial Output Timing Diagram
Elite Semiconductor Memory Technology Inc.
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ESMT
CE
(Preliminary)
F25L32QA
SCK
SO
SI
HOLD
Figure 32: HOLD Timing Diagram
VCC VCC (max)
Program, Erase and Write command is ignored CE must track VCC
VCC (min) Reset State VWI TPUW TVSL Read command is allowed Device is fully accessible
Time
Figure 33: Power-Up Timing Diagram
Table 17: Power-Up Timing and VWI Threshold
Parameter VCC(min) to CE low Time Delay before Write instruction Write Inhibit Threshold Voltage Note: These parameters are characterized only. Symbol TVSL TPUW VWI 1 Min. 200 10 2 Max. Unit us ms V
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ESMT
(Preliminary)
F25L32QA
Input timing reference level 0.8VCC 0.7VCC 0.3VCC AC Measurement Level
Output timing reference level
0.5VCC
0.2VCC
Note : Input pulse rise and fall time are <5ns
Figure 34: AC Input/Output Reference Waveforms
Figure 35: A Test Load Example
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ESMT
PACKING DIMENSIONS
(Preliminary)
F25L32QA
8-LEAD SOIC 200 mil ( official name - 209 mil )
8
5
E1
1
b e
4
D
A2
A
E
L A1 L1
SEATING PLANE
DETAIL "X"
Dimension in mm Symbol Min A A1 A2 b c D --0.05 1.70 0.36 0.19 5.13 Norm --0.15 1.80 0.41 0.20 5.23 Max 2.16 0.25 1.91 0.51 0.25 5.33
Dimension in inch Symbol Min --0.002 0.067 0.014 0.007 0.202 Norm --0.006 0.071 0.016 0.008 0.206 Max 0.085 0.010 0.075 0.020 0.010 0.210 E E1 L e L1
Dimension in mm Min 7.70 5.18 0.50 Norm 7.90 5.28 0.65 1.27 BSC 1.27 1.37 --1.47 8 Max 8.10 5.38 0.80
Dimension in inch Min 0.303 0.204 0.020 Norm 0.311 0.208 0.026 0.050 BSC 0.050 0.054 --0.058 8 Max 0.319 0.212 0.032
0
0
Controlling dimension : millimenter
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ESMT
PACKING 16-LEAD
16
(Preliminary) DIMENSIONS SOIC ( 300 mil )
9
F25L32QA
E1
A E
L DETAIL "X"
1
b D
e
8
0.25
GAUGE PLANE
A2 A
SEATING PLANE
Dimension in mm Symbol Min A A1 A2 b c D --0.1 2.05 0.31 0.20 10.10 Norm ----------10.30 Max 2.65 0.3 --0.51 0.33 10.50
Dimension in inch Symbol Min --0.004 0.081 0.012 0.008 0.400 Norm ----------0.406 Max 0.104 0.012 --0.020 0.013 0.413 E E1 L e
A1
"X"
Dimension in mm Min Norm 10.30 BSC 7.50 BSC 0.40 --1.27 BSC 1.27 Max
Dimension in inch Min Norm 0.406 BSC 0.295 BSC 0.016 --0.050 BSC 0.050 Max
0
---
8
0
---
8
Controlling dimension : millimenter
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Publication Date: Jan. 2009 Revision: 0.2 40/42
C
0
ESMT
Revision History
Revision 0.1 Date 2008.07.02
(Preliminary)
F25L32QA
Description Original 1. 2. 3. 4. 5. 6. Add 16-pin SOIC package Add the specification of 86MHz Modify the size of OTP security sector Modify typo error Modify headline and the specification of TCE Delete TBP1 and the rating of Temperature Under Bias
0.2
2008.01.13
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ESMT
All rights reserved.
(Preliminary) Important Notice
F25L32QA
No part of this document may be reproduced or duplicated in any form or by any means without the prior permission of ESMT. The contents contained in this document are believed to be accurate at the time of publication. ESMT assumes no responsibility for any error in this document, and reserves the right to change the products or specification in this document without notice. The information contained herein is presented only as a guide or examples for the application of our products. No responsibility is assumed by ESMT for any infringement of patents, copyrights, or other intellectual property rights of third parties which may result from its use. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of ESMT or others. Any semiconductor devices may have inherently a certain rate of failure. To minimize risks associated with customer's application, adequate design and operating safeguards against injury, damage, or loss from such failure, should be provided by the customer when making application designs. ESMT's products are not authorized for use in critical applications such as, but not limited to, life support devices or system, where failure or abnormal operation may directly affect human lives or cause physical injury or property damage. If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications.
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